Dynamic Random Access Memory (DRAM) cells can retain information only temporarily, on the order of milliseconds, even with power continuously applied. Therefore, the cells must be read and refreshed at periodic intervals. Although the storage time may appear to be short, it is actually long enough to allow many memory operations to occur between refresh cycles. The advantages of cost per bit, device density, and flexibility of use (i.e., both read and write operations are possible) have made DRAM cells the most widely used form of semiconductor memory to date. The earliest DRAM cells were three-transistor cells. Today, DRAM cells consisting of only one transistor and one capacitor have been implemented.
When forming semiconductor devices such as a DRAM cell having high aspect ratio features (i.e., the depths of recesses in the device surface are many times greater than the widths of the recesses), it is difficult to form a uniform resist layer across the device surface. Conventional "spin coating" methods are unsuccessful because, after application, the coated material undergoes a volume change during solvent evaporation and material densification. The shrinkage, due to volume change, draws material down into the features causing the coated material to be pulled down, thereby thinning the coated material in areas of high pattern density.
These non-uniformities are problematic when the resist is subsequently etched to form a recessed barrier or stopping layer of controlled and uniform depth. Such a barrier or stopping layer might be formed, for example, in the fabrication of a DRAM device to define vertical features into each trench in an array, such as to form a buried dopant out-diffusion of controlled depth, or to define the length of junctions and gate electrodes in a vertical transistor.
During such processing, variations in the thickness of the starting, top layer result in undesirable cross-wafer variations in recess depth. The amount of process variation within a chip and across a wafer for the resist recess process depends mainly upon: (1) the etch rate profile within a chip and across a wafer, and (2) the resist profile within a chip and across a wafer.
Referring to FIGS. 1 and 2, during solvent evaporation and material densification, the shrinkage of a resist 10, due to volume change, draws material down into a plurality of trenches 12 in a wafer 14. The result is non-uniform depths with the degree of variation in depth indicated by arrows 16 in FIG. 2. Without precise and uniform control over vertical depths, device dimensions cannot be controlled accurately across the wafer, or even within the chip.
A variety of suggestions have been offered for solving this problem. Viscosity, spin speeds, baking and curing conditions and thickness all have been varied in attempts to improve the uniformity of the coating from the center to the edge of the wafer. However, significant center-to-edge thickness variation and pattern factor variation are still present.
Attempts to planarize the resist after baking are known. For example, chemical-mechanical planarization processes such as Chemical-Mechanical Polishing (CMP) have been applied. The results of these attempts have not been fully qualified. Moreover, the addition of a chemical mechanical planarization step adds greatly to production costs.
Resist planarization, using exposure methods, also has been proposed. An exposure step requires additional equipment, however, such as a photolithography tool or a flood exposure system. "Photolithography" is a process in which a light source illuminates a pattern and projects the image through a lens assembly onto a semiconductor wafer or substrate. Ultimately, the pattern is etched into the wafer. Such additional equipment results in additional production costs.
There remains a need, therefore, for an improved method of forming a resist layer of uniform thickness across a surface patterned with a varying density of high aspect ratio features. It is an object of the present invention to provide a new and improved method of resist filling and planarization for the fabrication of semiconductor devices. It is another object of the present invention to provide a method of resist filling and planarization for the fabrication of semiconductor devices that eliminates, or at least greatly reduces, center-to-edge thickness variations in the resist coating that is applied during the fabrication of the semiconductor devices. It is a further object of the present invention to provide a method of resist filling and planarization for the fabrication of semiconductor devices that does not add greatly to the cost of fabrication of the semiconductor devices. It is still another object of the present invention to provide a method of resist filling and planarization for the fabrication of semiconductor devices that does not require the use of additional, expensive equipment in the fabrication of the semiconductor devices.